1. Field of the Invention
The present invention relates to a solid-state imaging device for use as a linear sensor comprising a linear array of photoelectric transducer elements or an area sensor comprising a three-dimensional matrix of photoelectric transducer elements.
2. Description of the Related Art
Heretofore, solid-state imaging devices, e.g., CCD (charge-coupled device) linear sensors, employ two-phase transfer clocks for transferring electric charges primarily because the driver circuit used is simple in arrangement and the two-phase transfer clocks are suitable for high-speed charge transfer.
FIG. 1A of the accompanying drawings shows a general structure of an IC-implemented CCD linear sensor 1 employing two-phase transfer clocks.
As shown in FIG. 1A, the CCD linear sensor 1 includes a photosensor 2 composed of a linear array of about 5000 photoelectric transducer elements. The odd-numbered photoelectric transducer elements PO (P1, P3, . . . ) of the photosensor 2 are connected through a readout gate electrode 4 to a CCD register .alpha.25, and the even-numbered photoelectric transducer elements PE (P2, P4, . . . ) of the photosensor 2 are connected through the readout gate electrode 4 to a CCD register .beta.26. The readout gate electrode 4 is connected to an input terminal 17 which supplies readout gate pulses .phi.TG.
The CCD register .alpha.25 comprises an array of registers which are connected alternately to an input terminal 18 which supplies a clock signal .phi.1 and an input terminal 19 which supplies a clock signal .phi.2. The final register on the output end of the CCD register .alpha.25 is connected to an input terminal 20 which supplies a clock signal .phi.2L. Signal charges are transferred to a floating diffusion region 3 of the CCD register .alpha.25. The floating diffusion region 3 has an output terminal connected through a buffer 8 to an output terminal 22 where a signal V1 appears.
The CCD register .beta.26 comprises an array of registers which are connected alternately to an input terminal 16 which supplies a clock signal .phi.1 and an input terminal 15 which supplies a clock signal .phi.2. The final register on the output end of the CCD register .beta.26 is connected to an input terminal 14 which supplies a clock signal .phi.1L. Signal charges are transferred to a floating diffusion region 5 of the CCD register .beta.26. The floating diffusion region 5 has an output terminal connected through a buffer 9 to an output terminal 12 where a signal V2 appears.
The floating diffusion regions 3, 5 are also connected to the sources of respective FETs (field-effect transistors) 6, 7. The FETs 6, 7 have respective gates, i.e., reset gates, connected to input terminals 21, 13, respectively, which supply reset gate pulses (also referred to as reset gate clock pulses) .phi.R1, .phi.R2. The FETs 6, 7 have respective drains connected to a common input terminal 11 which supplies a power supply voltage V.sub.DD.
Operation of the CCD linear sensor 1 shown in FIG. 1A will be described below.
FIGS. 2A through 2H are timing charts illustrative of the manner in which the CCD linear sensor 1 shown in FIG. 1A operates.
When a readout gate pulse .phi.TG shown in FIG. 2A which corresponds to a line clock signal is supplied through the input terminal 17 to the readout gate electrode 4, electric charges stored in the photoelectric transducer elements PO, PE of the photosensor 2 are transferred at once to the CCD registers .alpha.25, .beta.26, respectively.
Then, when two-phase transfer clock signals .phi.1 (.phi.1L), .phi.2 (.phi.2L) shown in FIGS. 2B and 2C are supplied to the registers of the CCD registers .alpha.25, .beta.26 through the input terminals 18, 16, 14 and the input terminals 19, 15, 20, the electric charges that have been transferred from the photosensor 2 to the registers of the CCD registers (.alpha.25, .beta.26 are successively transferred to the output ends thereof. The electric charges are transferred to the floating diffusion regions 3, 5 and converted thereby into respective voltage signals, which are supplied as output signals V1, V2 in opposite phase with each other (see FIGS. 2F and 2G) through the respective buffers 8, 9 to the respective output terminals 22, 12.
After the electric charges have been converted into voltage signals by the floating diffusion regions 3, 5, any remaining electric charges in the floating diffusion regions 3, 5 are drained to the common input terminal 11 through the FETs 6, 7 in response to reset gate pulses .phi.R1, .phi.R2 (see FIGS. 2D and 2E) that are applied from the input terminals 21, 13 to the gates of the FETs 6, 7.
As can be understood from FIGS. 2H, 2F, and 2G, the CCD linear sensor 1 has 8-bit photoelectric transducer elements P1.about.P8 for a black reference on its output end, 22-bit photoelectric transducer elements P9.about.P30 for an optical black reference, 2-bit ineffective photoelectric transducer elements P31, P32, 5000-bit effective photoelectric transducer elements P33.about.P5032, 2-bit ineffective photoelectric transducer elements P5033, P5034, and 3-bit dummy photoelectric transducer elements P5035.about.P5037.
Each of the output signals V1, V2 produced by the CCD linear sensor 1 includes low levels, referred to as signals S, that correspond respectively to the effective photoelectric transducer elements P33.about.P5032 of the CCD linear sensor 1. The period of each of the signals S is referred to as a signal period T.
FIG. 3 of the accompanying drawings illustrates a CCD linear sensor 31 and a signal processing circuit 30 connected thereto, the CCD linear sensor 31 being identical to the CCD linear sensor 1 shown in FIG. 1A;
In FIG. 3, signals S of output signals V1, V2 from the CCD linear sensor 31 are sampled and held by respective sample and hold circuits 34, 35 connected respectively to output terminals 32, 33 of the CCD linear sensor 30 in response to sample and hold pulses SH1, SH2 that are supplied in opposite phase with each other from respective terminals 36, 37 to the sample and hold circuits 34, 35. Thereafter, the sampled and held signals S are converted by a common analog-to-digital (A/D) converter 38 connected to the sample and hold circuits 34, 35 into a digital signal, which is then supplied to an output terminal 39 for use by an external device.
In applications using solid-state imaging devices such as CCD linear sensors, it is often indispensable to achieve real-time signal processing and high image quality.
To meet real-time signal processing requirements, solid-state imaging devices are required to increase the frequency and speed of clock signals that are used. It is also necessary that the signal S contain low noise in order to satisfy requirements for high image quality.
As can be seen from FIGS. 1A and 2A through 2H, the clock signals that are required to output the signal V1 include the pulses .phi.TG, .phi.1, .phi.2 (.phi.2L), .phi.R1, but not the pulses .phi.1L, .phi.R2, and no pulses .phi.2L, .phi.R1 are required to output the signal V2.
The reset gate pulses .phi.R1, .phi.R2 are generated at such timing that they pose a problem with regard to meeting requirements for high image quality.
More specifically, as shown in FIGS. 2E and 2F, each of the reset gate pulses .phi.R2 which are not required to output the signal V1 has a negative-going edge (see the arrow indicated by X) in the signal period T of a signal S of the output signal V1, and as shown in FIGS. 2D and 2G, each of the reset gate pulses .phi.R1 which are not required to output the signal V2 has a negative-going edge (see the arrow indicated by Y) in the signal period T of a signal S of the output signal V1.
The negative-going edges of the reset gate pulses .phi.R1, .phi.R2 cause coupling-induced noise, i.e., noise N due to a clock overlap, in the signals S, which thus have a non-flat irregular waveform.
If the clock frequency is relatively low, then those periods of the signals S which suffer the noise N, i.e., suffer level fluctuations due to the contained noise N, and those signal periods which do not suffer such level fluctuations are spaced in time from each other. When the sampling timing (the sample and hold pulses SH1, SH2) of the sample and hold circuits 34, 35 is brought into conformity with the signal periods which do not suffer level fluctuations, no noise N is contained in the signals that have been sampled and held.
However, if the clock signals are supplied at a higher frequency and at a higher speed, the waveform of the signals S is caused to fluctuate in all the signal periods T thereof due to the noise N. At this time, inasmuch as the signals S have to be sampled and held during the signal periods T in which the signal waveform is fluctuating, the noise N is necessarily contained in the signals that have been sampled and held. As a result, it is impossible to achieve high image quality with such sampled signals S.